BitSim participates in this year’s first Smart Exploration project meeting. An EU-funded project that develops cost-effective, environmentally friendly tools and methods for geophysical exploration.
BitSim’s Andrea Leopardi gave a well attended presentation at the FPGA days in Stockholm regarding Accelerated (Embedded) Image Processing.
For you who have attended our talk, we hope you got exciting insights to accelerate the development of your next project on embedded systems.
For all the others, check our article here.
This core offloads an embedded processor with the communication accelerated in the FPGA, with more than ~900+ Mb/s of effective data transfer rate. Standard functions for transmit, receive, ARP-handling, AXI-stream and loop back are included.
Until today, more than 3,5 million devices with an on-board BADGE have been shipped, both as ASSP/processors and and as FPGA chips. BADGE is used in many areas: white goods, medtech equipment, alarms, trucks, busses, rear cameras, measurement equipment etc.
Flir Systems is using BitSim’s FPGA-IP, Bit-MIPI CSI-2 in their newly launched advanced thermal cameras. Read more.
The MIPI Alliance, the non-profit corporation that brings the mobile industry together, has standardized the interface between the camera/image sensor and the receiving electronics (host processor or similar) for further image processing, through a high-speed serial interface, the MIPI CSI-2.
The market for image sensors is increasing by over 10% annually, with the consumer and automotive markets leading this growth.
With MIPI CSI-2, the camera providers can reach the market faster with this standardized way of interacting with the sensors: at a faster speed, at a higher resolution, or more cost effectively.
Today, MIPI CSI-2 is also used in other areas, such as test and measurement, industrial or medical markets.
“BitSim has supported us in an exemplary way, and BitSim’s IP is one important part of the complete effort that made us reach the market faster in launching our new advanced thermal imaging cameras”, says Rikard hunell, Vice President Sourcing & Strategic Planning of Flir.
1-4 data lanes
AXI4-Stream Video output
D-PHY protocol decoding included
Full High Speed/Low Power mode support